Verilog HDL中always @ (*)中“*”指代的内容

The implicit event_expression, @*, is a convenient shorthand that eliminates these problems by adding all nets and variables that are read by the statement (which can be a statement group) of a proceduraltiming control_statement to the event_expression.

“*”指代，当前always语句块内的所有输入变量的变化

如下代码所示的定时器

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module Example_Style 
(
	CLK_50M,RST_N
);
input CLK_50M; 
input RST_N;
parameter SET_TIME_1S = 27'd50_000_000;
always @ (posedge CLK_50M or negedge RST_N) 
begin
	if(!RST_N) 
		time_cnt <= 27'h0; 
	else 
		time_cnt <= time_cnt_n;
end
always @ (*)
begin
	if(time_cnt == SET_TIME_1S) 
		time_cnt_n = 27'h0;
	else
		time_cnt_n = time_cnt + 27'h1;
end

always @ (*)中，“*”指代的是当前always中的敏感变量“time_cnt”，而不是全局的CLK_50M或RST_EN
即always @ (*) = always @ (time_cnt)